TITLE III
LAYOUT DESIGNS (TOPOGRAPHIES) FOR INTEGRATED CIRCUITS
Chapter I
Scope
90. The following definitions shall apply under this Law:
— layout design (topography) means the three-dimensional arrangement, whatever its
expression, of elements, at least one of which is an active component, and all or part of the
interconnections of an integrated circuit, or such a three-dimensional arrangement which is
prepared for an integrated circuit intended to be manufactured;
— integrated circuit : a product, in final or intermediate form, of which at least one
element is an active component and some or all of whose interconnections are an integral part
of the body and/or surface of a piece of material that is intended to be used electronically.
91. Layout designs (topographies) for integrated circuits which are original insofar as
they are the fruit of the intellectual effort of their creators and which, at the time of their
creation, are not common for the creators of layout designs (topographies) and manufacturers
of integrated circuits, may be protected as provided for by this Law.
A layout design (topography) for integrated circuits, which consists of a combination of
elements or interconnections that are common, shall only be protected if the combination,
considered as a whole, meets the conditions referred to in the above paragraph.
The protection granted to a layout design (topography) for integrated circuits shall only
apply to the layout design (topography) for integrated circuits as such, to the exclusion of any
concept, process, system, technique or coded information incorporated in this layout design.
Chapter II
Miscellaneous provisions
93. The provisions of Chapters II and II of Title II of this Law shall apply to layout
designs (topographies) for integrated circuits, subject to the special provisions below.
94. Any layout design (topography) for integrated circuits may give rise to an industrial
property title known as a “certificate of layout design (topography) for integrated circuits”.
Layout designs (topographies) for integrated circuits shall be protected for a period of
ten years from the date on which the corresponding application is filed.
95. The right to the title shall belong to the creator or his successors in title, subject to
the provisions of Article 18 above.
The provisions of Articles 19 and 20 above shall apply to layout designs (topographies)
for integrated circuits.
96. A request for a certificate for a layout design (topography) for integrated circuits
must be accompanied, when filed, by a copy or a drawing of the layout design (topography)
for integrated circuits and, where the integrated circuit has been used commercially, by a
sample of the integrated circuit, as well as information defining the electronic function which
the integrated circuit is intended to perform.
97. Unless the layout design is common, an application covered by Article 96 above
may not be filed two years after the first ordinary commercialization of said design in any part